PhD, Device Engineer at Intel Corporation

Alex Liu

Highly motivated and accomplished professional in semiconductor device, process integration and yield.  
•	Comprehensive knowledge of device physics: silicon/III-V logic devices and flash memory. 
•	Five-year experience of research on semiconductor devices. 
•	Eight-year industry experience of non-volatile memory, emerging memory product development.

Emerging memory pathfinding:
- Emerging memory pathfinding including architecture, device and material, Plan emerging memory technologies (3D Xpoint, NAND, MRAM, RRAM) to fit into organization's product roadmap.
- Designed pre-Si device specifications based on TCAD and partial experimental data allowing tape-out 3rd gen of 3DxP technology. 
- Identified root cause and developed fundamental solutions for reliability limiters of Optane memory cell.

Device Engineer and Memory Architect

Non-volatile memory R&D for 1st and 2nd gen Optane SSD and persistent memory (storage class memory).
- Innovated cell structure/material, write & read algorithm enabling the 1st die yield and continuous yield/reliability improvement.  
- Key inventor for core memory IPs. 
- Applied advanced statistics and machine learning for fast TD decisions and high volume manufacturing variation control.

Device Engineer

Projects: 
1. Non-planar tri-gate InGaAs quantum well high electron mobility transistors (HEMTs)

2. Low power InGaAs single electron transistors (SETs)

3. Device model development for low sub-threshold swing tunnel field-effect-transistors (TFETs)

Research Assistant/ Ph.D. Candidate

•	Process optimization of MOCVD high-k dielectric deposition on III-V semiconductors 
-	Characterized the MOS capacitors with high-k (HfO2/Al2O3) grown under various conditions in MOCVD chamber. Optimized deposition process based on interface trap density measurements