Alex Liu

PhD, Device Engineer at Intel Corporation

Santa Clara, CA, US

About

Highly motivated and accomplished professional in semiconductor device, process integration and yield. • Comprehensive knowledge of device physics: silicon/III-V logic devices and flash memory. • Five-year experience of research on semiconductor devices. • Eight-year industry experience of non-volatile memory, emerging memory product development.

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Work experience

  1. February 2017 – present

    Intel Corporation

    Device Engineer and Memory Architect
    Emerging memory pathfinding: - Emerging memory pathfinding including architecture, device and material, Plan emerging memory technologies (3D Xpoint, NAND, MRAM, RRAM) to fit into organization's product roadmap. - Designed pre-Si device specifications based on TCAD and partial experimental data allowing tape-out 3rd gen of 3DxP technology. - Identified root cause and developed fundamental solutions for reliability limiters of Optane memory cell.
  2. January 2014 – April 2017

    Intel Corporation

    Device Engineer
    Non-volatile memory R&D for 1st and 2nd gen Optane SSD and persistent memory (storage class memory). - Innovated cell structure/material, write & read algorithm enabling the 1st die yield and continuous yield/reliability improvement. - Key inventor for core memory IPs. - Applied advanced statistics and machine learning for fast TD decisions and high volume manufacturing variation control.
  3. August 2009 – December 2013

    Penn State University

    Research Assistant/ Ph.D. Candidate
    Projects: 1. Non-planar tri-gate InGaAs quantum well high electron mobility transistors (HEMTs) 2. Low power InGaAs single electron transistors (SETs) 3. Device model development for low sub-threshold swing tunnel field-effect-transistors (TFETs)
  4. July 2008 – August 2009

    National University of Singapore

    Graduate Research Assistant
    • Process optimization of MOCVD high-k dielectric deposition on III-V semiconductors - Characterized the MOS capacitors with high-k (HfO2/Al2O3) grown under various conditions in MOCVD chamber. Optimized deposition process based on interface trap density measurements

Education

  1. Present

    shandong exp mid school

  2. 2009 – 2013

    Penn State University

    Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering
  3. 2008 – 2009

    National University of Singapore / NUS

    Electrical and Electronics Engineering
  4. 2004 – 2008

    Peking University

    Bachelor of Science (BS), Physics